ITRS Working Group Models
We will be posting these links soon. Thank you for your patience...
Roadmap modeling programs will be available to download for your use.
MASTAR
The Model for Assessment of cmoS Technologies And Roadmaps (MASTAR) application allows the user to evaluate immediately the impact of these technological parameters on the main transistor characteristics such as the threshold behavior, performance values or time delay. Moreover, the influence of “physical” secondary parameters such as mobility, poly depletion and dark space can be visualized giving a deep insight in the physics of CMOS devices.
NanoHub
More than Moore White Paper by the IRC
This white paper proposes a methodology to help the ITRS community identify those More than Moore (MtM) technologies for which a roadmapping effort is feasible and desireable.
Assembly and Packaging White Paper on System Level Integration
System on Chip (SoC) and System in Package (SiP) technologies provide a path for continued improvement in performance, power, cost and size at the system level without relying upon conventional CMOS scaling alone. System in Package (SiP) technology is rapidly evolved from specialty technology used in a narrow set of applications to a high volume technology with wide ranging impact on electronics markets. This paper presents details on requirements, challenges, and applications for SiP.
We will be posting these links soon. Thank you for your patience...
Roadmap modeling programs will be available to download for your use.
MASTAR
The Model for Assessment of cmoS Technologies And Roadmaps (MASTAR) application allows the user to evaluate immediately the impact of these technological parameters on the main transistor characteristics such as the threshold behavior, performance values or time delay. Moreover, the influence of “physical” secondary parameters such as mobility, poly depletion and dark space can be visualized giving a deep insight in the physics of CMOS devices.
NanoHub
More than Moore White Paper by the IRC
This white paper proposes a methodology to help the ITRS community identify those More than Moore (MtM) technologies for which a roadmapping effort is feasible and desireable.
Assembly and Packaging White Paper on System Level Integration
System on Chip (SoC) and System in Package (SiP) technologies provide a path for continued improvement in performance, power, cost and size at the system level without relying upon conventional CMOS scaling alone. System in Package (SiP) technology is rapidly evolved from specialty technology used in a narrow set of applications to a high volume technology with wide ranging impact on electronics markets. This paper presents details on requirements, challenges, and applications for SiP.